1. Field of the Invention
The present invention relates to a method and apparatus for testing circuit.
2. Description of the Related Art
Nowadays, enormous amounts of semiconductor devices are manufactured. The manufactured semiconductor device needs to be tested regarding the existence of a defect by the circuit tester, before shipping to the market. The circuit tester performs a test called a function test to a semiconductor device, and judges the quality thereof. In the function test, a test pattern is supplied to the semiconductor device and the quality is judged based on an output result from the semiconductor device.
In recent years, research for high integration of the semiconductor devices is advanced actively. With high integration of the semiconductor device, the test pattern for the function test has become more complicated and production of the test pattern has become more difficult. In addition, if all elements are to be tested perfectly by the function test about all possibilities of defects, since the amount of test patterns are enormous, it takes time for testing too much and such a function test is almost impossible.
There is a method called quiescent supply current test which measures quiescent supply current of the semiconductor device as a test method for efficient testing which has developed apart from the function test. This method is characterized by judging the quality of the semiconductor device by detecting abnormal current in a quiescent state, using the principle in which a normal transistor hardly allows current to pass in a quiescent state. However, since a design rule becomes fine and especially becomes in the order of 0.1 micrometer or less, leakage current increases and current difference between a normal device and a defective device becomes small. Therefore, it is considered that it is difficult to test the circuit which has such a fine pattern using the conventional quiescent supply current test method.
Moreover, in the conventional quiescent supply current test, in order to observe a current waveform, it is necessary to lower a test clock rate from a clock rate at the time of real operation. For example, when a semiconductor device is tested with clock rate at the time of real operation of several hundreds megahertz, it is difficult to observe a current waveform sufficiently accurately unless the test clock rate is lowered between several kilohertz and several tens kilohertz in the quiescent supply current test. Therefore, there has been a problem that the conventional quiescent supply current test requires long time.